Location: Vienna (On-site / Hybrid)
Division: R&D
Reporting Line: Head of R&D (Line Manager); SW Team Lead (Functional Lead)
About PIDSO
For over 15 years, PIDSO has been developing high-performance communication solutions “Made in Austria” – built for environments where failure is not an option.
Our antenna and RF systems enable reliable data transmission and signal processing in mission‑critical applications across aerospace, defense, motorsport, automotive, and Industry 4.0.
We combine research, development, manufacturing, and testing under one roof. Fast, focused, and with uncompromising attention to detail.
Tasks
The Mission
Working closely with our Lead DSP Architect, you will contribute across the full signal processing workflow — from algorithm evaluation and simulation to deterministic, real‑time execution on Zynq‑7000 and MPSoC platforms. Depending on your background, you will be expected to engage at both the algorithmic and implementation level: understanding the mathematics behind what you implement, not just the code.
Key Responsibilities
* Algorithm Development: Participate in algorithm design, feasibility analysis, and simulation (Python/MATLAB) for tasks including filtering, estimation, sensor fusion, and SDR.
* Embedded Deployment: Implement and optimize DSP algorithms in C/C++ for ARM Cortex‑A/R; apply NEON/SIMD intrinsics and cache‑aware memory strategies where required.
* Verification: Design and maintain test suites validating embedded output against golden models.
* FPGA Interface: Integrate DSP logic with FPGA IP cores over AXI/DMA in collaboration with the hardware team.
* Product Improvement: Identify algorithmic or implementation bottlenecks in existing products and drive targeted improvements.
Requirements
Your Profile
* Education: MSc or PhD in Electrical Engineering, Communications Engineering, or a related field with strong signal processing content. Equivalent industry experience considered.
* DSP Depth: Strong theoretical and applied knowledge — fixed‑point arithmetic, spectral analysis/FFT, estimation theory, adaptive filters, Kalman filtering. You are comfortable deriving before implementing.
* Implementation Skills: Production‑level C/C++; Python or MATLAB for simulation and verification. Familiarity with Git and CI/CD pipelines.
* Embedded Experience: Solid understanding of SoC architecture (ideally Xilinx Zynq/MPSoC), memory hierarchy, and RTOS concepts. FPGA/RTL exposure is a plus, not a requirement.
* Mindset: You are comfortable owning the gap between a mathematical model and a resource‑constrained system — and are bothered when the two don't match.
* Domain Interest: Background or genuine curiosity in antenna systems, software‑defined radio, or radar is a meaningful plus.
* Experience: 3+ years in a DSP‑focused role or equivalent academic/research background with hands‑on embedded exposure.
Benefits
Join a small, highly capable engineering team building RF technology that performs when failure is not an option. Work at the intersection of advanced signal processing, embedded systems, SoC architectures, and real‑world physics — where mathematical models meet resource‑constrained hardware and engineering decisions have a tangible impact.
At PIDSO, you will work alongside experienced experts, move fast without corporate overhead, and contribute directly to mission‑critical communication and radar technologies developed and manufactured in Austria.
Salary
For this position, the minimum salary according to the Kollektivvertrag Metallgewerbe (Verwendungs‑gruppe III, 6 years) is € 3 300,16 gross per month, with a clear willingness to overpay based on your existing projects and technical skills.
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