Senior Staff Engineer, Mixed Signal Layout We are seeking a senior staff engineer to lead mixed‑signal layout on RF and SerDes projects for high‑frequency solutions.
Responsibilities Execute full‑custom IC and block‑level layout from schematic to tape‑out for high‑frequency RF blocks and high‑speed SerDes components.
Implement precise matching and isolation techniques to prevent noise coupling.
Run and debug full‑chip physical verification (DRC, LVS, ERC, antenna rules).
Analyze and minimize parasitic resistances, capacitances, and inductances for signal and power integrity.
Floorplan, pad‑ring assembly, and final chip integration with ESD, latch‑up, and electro‑migration guidelines.
Provide technical leadership and mentor junior layout engineers.
Qualifications University degree in Electrical Engineering or comparable discipline.
5+ years hands‑on experience in CMOS and FinFET semiconductor technologies.
Proven track record in analog/RF IC layout, including PCIe, Ethernet, USB, or custom SerDes at multi‑gigabit data rates.
Strong proficiency with industry‑standard EDA tools (Cadence Virtuoso, Siemens Calibre, etc.).
Excellent analytical, problem‑solving, and debugging skills.
Strong communication and collaboration skills across multidisciplinary teams.
Leadership abilities to guide a small layout team.
Fluent in English.
Compensation & Benefits Competitive salary and additional benefits based on experience and qualification. Employment follows the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H. Salary is paid 14 times per year. Higher compensation is possible depending on expertise and skills.
We provide equal employment opportunities and welcome diversity and inclusion.
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