Overview
Chipright seeks highly motivated and experienced Analog Layout development engineer to work on Memory IPs.
Responsibilities
* Work on Memory IPs and top level layout of test chips.
* Coordinate tapeout procedures for internal and external foundries.
* Main layout focus: memories and supporting blocks, ADC/DAC, and testchip placement.
* Adapt IP blocks and support integration into key projects.
* Maintain strong communication with interfaces such as Process Development, Design, Test Development, Production, and Quality.
Qualifications
* 7+ years minimum experience in physical layout.
* Experience working with Memory IPs, and top level layout of test chips.
* Proficient with Cadence design and layout environment.
* Knowledge of LayoutXL; Calibre/Assura is a plus.
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