A leading semiconductor solutions provider seeks a Senior Staff Engineer for Digital Verification to define verification plans, lead projects, and mentor peers. Ideal candidates should have over 6 years of experience in digital verification and be proficient in SystemVerilog, UVM, and relevant verification tools. The successful applicant will work collaboratively with designers and contribute to innovative methodologies. This position is located in Villach, Kärnten, Austria and offers competitive salaries and benefits.
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